Abstract / truncated to 115 words (read the full abstract)

The implementation of wireless transceivers on a single chip in a single technology requires digital realizations of traditional analog building blocks such as phase-locked loops (PLLs). All-digital PLLs (ADPLLs) utilize the zero crossings of signals instead of their amplitudes to realize the frequency synthesizer entirely in digital CMOS technology. This thesis analyzes ADPLLs and highlights the system-level signal processing aspects. A z-domain model and a mixed-signal model are used to develop signal processing algorithms, to perform high-level simulations, and to evaluate the performance of ADPLLs. The impact of imperfections on the output phase noise spectrum are analytically described and compared to event-driven simulation outcomes. Oscillator noise, frequency quantization noise with sigma-delta noise shaping, and reference ... toggle 6 keywords

ADPLL – PLL – time-to-digital converter tdc – sigma-delta noise shaping – modelling and simulation – spurs

Follow @eurasip