Abstract / truncated to 115 words (read the full abstract)

Modern signal processing applications emerging in telecommunication and instrumentation industries need high-speed analog-to-digital converters (ADCs), which can be achieved by employing a time-interleaved parallel array of ADCs (time-interleaved ADCs). The time interleaving of the channels allows to increase the sampling rate by the number of channels compared to a single channel. Unfortunately, time-interleaved ADCs suffer from channel mismatches that limit their performance, wherefore this thesis deals with the identification and compensation of channel mismatches in time-interleaved ADCs. By using nonlinear hybrid filter banks, we have modeled and analyzed channel mismatches in detail. The model covers linear and nonlinear channel mismatches, unifies, and extends the channel models found in the literature. A novel foreground channel mismatch ... toggle 5 keywords

system modeling – system identification – calibration algorithms – time-interleaved – ADC

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