Abstract / truncated to 115 words (read the full abstract)

This doctoral thesis aims at optimising the floating-point implementations of signal processing algorithms on reconfigurable hardware with respect to accuracy, hardware resource and execution time. It is known that reduced precision in floating-point arithmetic operations on reconfigurable hardware directly translates into increased parallelism and peak performance. As a result, efficient implementations can be obtained by choosing the minimal acceptable precision for floating-point operations. Furthermore, custom-precision floating-point operations allow for trading accuracy with parallelism and performance. We use Affine Arithmetic (AA) for modeling the rounding errors of floating-point computations. The derived rounding error bound by the AA-based error model is then used to determine the smallest mantissa bit width of custom-precision floating-point number formats needed for ... toggle 10 keywords

floating-point arithmetic – signal processing – affine arithmetic – efficient implementation – reconfigurable computing – speech processing – algorithms – numerical analysis – bit width allocation – error analysis

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