Parallelized Architectures for Low Latency Turbo Structures (2007)
Abstract / truncated to 115 words
In this thesis, we present low latency general concatenated code structures suitable for parallel processing. We propose parallel decodable serially con- catenated codes (PDSCCs) which is a general structure to construct many variants of serially concatenated codes. Using this most general structure we derive parallel decodable serially concatenated convolutional codes (PDSC- CCs). Convolutional product codes which are instances of PDSCCCs are studied in detail. PDSCCCs have much less decoding latency and show al- most the same performance compared to classical serially concatenated con- volutional codes. Using the same idea, we propose parallel decodable turbo codes (PDTCs) which represent a general structure to construct parallel con- catenated codes. PDTCs have much less latency compared to classical ...
iterative decoding – concatenated codes – soft decision decoding al- gorithms – parallel processing – decoding latency – memory collision – turbo equal- ization – trellis coded modulation – space time trellis coding
Information
- Author
- Gazi, Orhan
- Institution
- Middle East Technical University
- Supervisor
- Publication Year
- 2007
- Upload Date
- Dec. 7, 2009
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